1. Field of the Invention
The present invention relates in general to the field of digital electronics, and more particularly to an arrangement for implementing the testing and verification of digital circuits after manufacture.
2. Description of the Prior Art
Typically, in the manufacture of digital electronic systems, circuit assemblies are first given an "In-Circuit" test after they have been assembled. This test attempts to individually verify each component in a circuit assembly, and its connections. The intent of this test is to verify that there are no manufacturing defects present. Other functional tests follow the In-Circuit test to verify the assembly's total operation.
When a digital circuit device is In-Circuit tested, its inputs are driven with a specific set of patterns or vectors and its outputs observed that they comply with an expected pattern. For SSI (Small Scale Integration) and some MSI (Medium Scale Integration) circuit devices this testing method does not present a problem. However, for hybrids, larger MSI, LSI (Large Scale Integration) circuit devices, ASICs (Application Specific Integrated Circuits) and USICs (User Specific Integrated Circuits) such as electronically programmable logic devices, testing in this manner is difficult. The number of test patterns or vectors required to completely test these complex devices are inherently very large. The number of patterns required to simply exercise each input and output of the circuit device, are extremely large and cumbersome and usually have to be manually generated.
In order to completely exercise a device, a complete logic state sequence must be provided to the circuit device under test. It is very difficult to reliably apply these large test patterns. This is due to the necessity to force other digital devices, that are co-located on the substrate and that drive the device under test, to logic states that are opposite to their current state. The above process is called "backdriving" or "overdriving", and can only be done for a limited time without harming the backdriven device. Therefore, the long testing sequences required for large and complex circuit devices can not be used without harming the circuit device under test.
One method employed in addressing the above mentioned problem is to use special testing sequences which use fewer vectors. As a result, the test typically does not fully exercise the device inputs and outputs and therefore, can not catch all the faults that may be present.
Another method of testing large digital circuit devices is the implementation of special circuitry in the device to provide a test mode. The test mode allows the device to be verified in some manner with a limited number of patterns. An example of this approach is the addition of multiplexers in series with the inputs and demultiplexers in series with the device outputs. The multiplexers are connected in such a way as to allow bypassing of the original internal device circuitry when in a test mode. In this manner an output of a device can be directly controlled by a selected corresponding input. This system works well as long as the number of input pins of a device are equal to the number of output pins. If the number of inputs and outputs are not equal, then additional circuitry is required to share pins. As a result, this method adds a significant amount of complexity and overhead to a digital circuit device.
One other example of added test circuitry, is the proposal by JTAG (Joint Test Action Group). The proposal, which is primarily intended for integrated circuits, involves implementing a scan shift register circuit for each input and output of a digital circuit device. Thereby, through a SCAN-IN test pin, a test pattern of 1s and 0s may be shifted into the shift register. The pattern subsequently appears on the device output pins. Further, the logic levels present on a circuit device's input pins can be latched and shifted out of a SCAN-OUT test pin. In this manner, a simpler set of test vectors can exercise each circuit device pin and check its connection to the surrounding circuit. The circuitry that is added in all test systems such as the above described JTAG proposal is independent of the sequence of input and output pins of a circuit device. Also, the JTAG proposal requires several device pins to support its functions as well as requiring a significant amount of circuit device "area" for inclusion of the test circuitry.
Accordingly, it is an object of the present invention to provide a test support circuit, which is added to a digital circuit device, and provides a method for easily verifying that the circuit device input and output circuits are correctly connected and operating properly.